The present invention relates to the field of integrated circuit manufacturing, and, more particularly, to interconnection line protection devices to protect elements connected to these lines against electrostatic charges generated during the manufacture of the integrated circuit. It is especially related to integrated circuits including MOS technology memories such as, for example, DRAM, NVRAM, EPROM, EEPROM or FLASH EPROM memories.
In the usual memory architecture, which is the matrix architecture, each cell is controlled by a bit line and a word line of the memory. The bit lines and the word lines are driven by the outputs of a decoder. Each cell can thus be read or written individually through the selection of the corresponding bit line and word line by an address decoding circuit of the memory.
However, it is also common to provide for word access to the memory. The common memory architectures thus provide for the possibility of simultaneously accessing several bits, typically 8, 16 or 32 bits. In any case, the basic unit in terms of memory word is the byte formed by 8 bits. Memory architectures are thus based on bytes, the eight corresponding memory cells being located on the same word line. A simplified drawing of this matrix architecture of the memories is shown in FIG. 1. In an architecture of this kind, the bit lines Bl, which are driven by the column decoder DECX and contact the drains of the MOS transistors, are metal (aluminum) lines. The word lines Wl, which are driven by the row decoder DECY and contact the gates of MOS transistors, are polysilicon lines. These interconnection lines travel throughout the memory array, longitudinally (0y) for the bit lines and horizontally (0x) for the word lines.
In this architecture, a byte is formed by eight cells located on one and the same word line Wl, at the intersection of eight consecutive bit lines. The usual EEPROM memory architectures also have source lines, made of metal, that contact the source diffusions of the memory cells to draw these sources to ground, generally in read mode. These source lines travel through the memory array longitudinally. They are commonly made of metal. They are connected peripherally to the memory array of a ground connection transistor controlled by a control signal as a function of the mode of access to the memory.
To enable the simultaneous selection of all the bits of a word on a word line and only these bits, a grouping of bit lines and columns is combined with the matrix organization. This enables simultaneous access to several cells, typically eight cells, forming a memory word (byte). An architecture of this kind calls for additional transistors each enabling the selection of a particular column of the memory. In this case, there is provided one control line per column, namely per group of eight bit lines, with one column selection transistor per word line. These control lines also run through the memory array longitudinally. They are usually made of metal.
In the case of a matrix architecture of this kind with columnwise grouping, one source line is generally provided for two columns. This source line connects the sources of the floating-gate transistors of the memory cells of these two columns to a corresponding ground connection transistor. The number of these ground connection transistors typically depends on the memory architecture chosen by the designer, in line with the application constraints and the design and drawing rules.
Thus, an EEPROM memory array usually includes, as interconnection lines running throughout the memory array (in one dimension of the array), bit lines, word lines, control lines and source lines. FIG. 2 shows two columns of a corresponding EEPROM memory array. This example shows the cells of two consecutive columns located on one and the same word line Wlk. It will be recalled that an EEPROM memory cell usually includes (at least) one access transistor Ta series-connected with a floating-gate transistor Tf. The access transistor is connected at its gate to the corresponding word line and at its drain to the corresponding bit line.
In the example, the first column Col1 has eight cells C0 to C7 placed on the word line Wlk. The first cell C0 is connected to the bit line Bl0, the second cell C1 is connected to the bit line Bl1 and so on and so forth up to the last cell C7 which is connected to the bit line Bl7. All the floating-gate transistors of these cells C0 to C7 have a common source diffusion connected to the source line associated with the column, LSi. A column selection transistor TCk,i is connected between the control line CGi associated with the column and the common gate of the floating-gate transistors of the cells C0 to C7.
The second column Col2 has an identical structure. In the example, it is made in the memory array in a symmetrical way. Thus, from left to right, there is the source line LSi of the first column, the eight bit lines B10 to B17, the control line CGi of the first column, the control line CGi+1 of the second column, eight bit lines Bl0 to Bl7 and the source line LSi+1 of this second column.
The problem that arises with such memory architectures lies in the different interconnection lines that run throughout the memory array in at least one direction of this array, Ox or Oy, and are connected to the cells. Indeed, it is well known that certain steps in the manufacture of an integrated circuit give rise to electrostatic charges that are collected by the interconnection lines forming an antenna. This may lead to an increase in potential at these lines that affects the elements connected thereto. In the example of the interconnection lines of a memory, the cells of this memory may be affected. Indeed, the increase in potential at the constituent elements of the memory cells may have different harmful effects.
A first harmful effect is the damaging or destruction of active elements of these cells: junctions, gate oxide, tunnel oxide, leading to leakages of these elements (junctions, gate oxide) or even breakdown (tunnel oxide). These harmful effects are generally found in any integrated circuit having interconnection lines connected to electronic elements. Another harmful effect is the reduction of the life cycle of the memory cell. The substantial increase in potentials on these lines due to the electrostatic charges may have the same effect as a large number of read and/or write access operations and may correspondingly reduce the lifetime guaranteed for these cells.
The manufacturing steps that raise these problems include, for example, the step of plasma etching of the polysilicon layers and of metallization and the steps for cleaning the wafers by gas flux or by liquid. In the plasma-etching step, the wafer is subjected to ion bombardment which may lead to an increase in the surface potential. Special precautions are usually taken to prevent this increase in potential, especially the application of a magnetic field in the etching chamber. However, these precautions prove to be insufficient in practice.
In the wafer-cleaning steps, the friction of the cleaning fluid may give rise to electrostatic charges, by triboelectricity. The prior art method of using a conductive fluid does not satisfactorily resolve this problem.
In certain integrated circuits, passive devices are also used. These are typically diodes connected between the interconnections and the substrate to limit the voltage incursion on these lines. The incursion is thus limited to the interconnection lines either by placing the diode in a forward connection with a limitation, in absolute value, to 0.6 volts or by placing the diode in an avalanche connection with a limitation, in absolute value, to 15 volts (typical values). However, these devices are not satisfactory, especially because they cannot be used for interconnection lines that have to receive high potentials in operational mode, namely potentials above the thresholds of the diodes, such as the interconnection lines of a memory array, for the programming of the cells.
Thus, an aim of the invention is to resolve the problem of electrostatic charges on the interconnection lines of an integrated circuit. This problem arises throughout the process of manufacturing the integrated circuit once the interconnection lines and their connections to elements of the integrated circuit have been made.
The approach used to resolve this problem is not to prevent these charges, as in the prior art, but to find a way of making the charges that might be generated during the manufacture of the integrated circuit flow away without damaging any of the elements connected to these interconnection lines.
The basic idea of the invention is a protection device that is active throughout the manufacture of an integrated circuit to protect an interconnection line.
The invention also relates to a device for the protection of an interconnection line of an integrated circuit, including a charge flow-off device connected to the interconnection line to be protected and a dummy interconnection line to activate the flow-off device, the protection device being active throughout the manufacture of the integrated circuit.
In practice, it is possible to provide for one and the same dummy interconnection line connected to several flow-off devices used for the protection of a set of interconnection lines. To obtain high efficiency, one and the same dummy interconnection line is connected to a limited number of flow-off devices so as not to damage the sensitivity of the dummy interconnection line.
In the exemplary application to a memory integrated circuit, it is possible especially to place dummy interconnection lines in the memory array to protect the different interconnection lines designed in the memory array to access the cells.